1. Field of the Invention
The present invention relates to an HDTV video decoder and more particularly to a method for controlling a memory interface in the HDTV video decoder.
2. Description of the Related Art
Generally, digital TV provides a superior picture quality on the TV receiver for the viewers. As a result, a growing interest in digital TV broadcasting has cultivated many efforts to compress video data for transmission and reproduction. Typically, a moving picture expert group (MPEG2) is used as the algorithm to compress video signals. Having a high compression rate ranging from approximately 1/40 to 1/60, the MPEG2 algorithm enables digital data transmission of high quality through general broadcasting channels to entertain viewers at home.
However, a digital TV receiver also requires a video decoder to restore the compressed data into the original video data of high picture quality. The digital TV receiver requires an enhanced video decoder capable of processing the highly compressed data. Thus, the video decoder for a digital TV processes data at a rate of approximately 5 to 6 times greater than the general quality video decoder as well as larger memories in order to decode the video data of high picture quality.
FIG. 1 shows a conventional video decoder in the related art designed to process video signals of normal resolution at a rate of approximately 15 MBytes per second. An input video bit stream transmitted by an encoder is variable length decoded at a variable length decoder (VLD) 11 and divided into a motion vector, a quantization value and a DCT coefficient. The DCT coefficient output by the VLD 11 is input to an inverse discrete cosine transformer (IDCT) 14 via an inverse scanner (IS) 12 and an inverse quantizer (IQ) 13.
The VLD 11 decodes the DCT coefficient into run levels. Particularly, one DCT block is composed of 8.times.8 coefficients, from which non-zero coefficients are the significant code information. The output run levels of the VLD 11 represent the size of the non-zero coefficients, namely the level and the number of zeros inserted between the non-zero coefficients. Accordingly, the run-level pair is converted to 64 continuous DCT coefficients by way of a run-level decoding process and output to the IS 12. In addition, to enhance the run-level code, the 8.times.8 coefficients are decoded in a zig-zagged scanning pattern during the data transmission from the lowest frequency component. Thus, the IS 12 converts the zigzagged scanning pattern to a raster scanning pattern.
The IQ 13 inverse-quantizes the inversed-scanned 64 DCT coefficients output from the IS 12 based on the quantization value, and outputs the result to the IDCT 14. The IDCT 14 performs IDCT on the inverse-quantized DCT coefficients and outputs the coefficients to a motion compensating section 15. The motion compensating section 16 restores the original picture using the video signals from the IDCT 14 and the motion vector separated from the VLD 11, and outputs the picture data to a display 16. Based upon the type of picture data, the display 16 rearranges the data prior to outputting the data or outputs the data directly without rearrangement.
The HDTV video decoder system based on the MPEG2 uses an external memory, composed of a buffer for temporarily storing a bit stream and at least two frame memories. Typically, DRAMs are used as frame memories. However, utilizing one memory for one IC is preferable in the construction of a decoder to reduce the number of pins and to efficiently utilize the remaining portion of the memory. To implement one memory for multiple uses, a variety of memory access request must be processed.
The memory in the video decoder has several roles including to read and write a bit stream, to read a data used for motion compensation, to write a decoded data, and to read a data to be displayed. Accordingly, the conventional video decoder includes a DRAM 22 and first in first outs (FIFOs) 17 to 20 for data transmission under the control of a memory control section 21 to prevent collisions among data in the bus in temporarily storing the data. The signals requested by the respective blocks are all require memory access to decode a video data and must be properly controlled for enhancing the decoding efficiency. Thus, the access time is divided for each access requests.
A conventional video decoder as shown in FIG. 1 has a low processing rate and may be suitable for processing a small amount of data, but it would be inapplicable as a HDTV video decoder which must process a large volume of data. Since the amount of data increases about 6 times for decoding a video data of the MPEG2 MP@HL, the data processing rate of the video decoder must be at least 93 MBytes per second. Moreover, other components must have a processing rate greater than 6 times the conventional video decoder shown in FIG. 1, with larger memory and higher data transmission rate.
FIG. 2 shows a video decoder that uses synchronous DRAMs (SDRAMS) capable of high speed memory access rather than using DRAMs as the external memory for greater data processing rate. The SDRAMs process input/output of data with higher processing rate relative to DRAMs because SDRAMS read/write the data in a pipe line by using an interleaving method.
The video decoder using the SDRAMS includes a bit stream buffer 51, a VLD buffer 52, MC buffer 53, a store buffer 54, and a display buffer 55 for the temporary data storage and communication rather than the FIFOs 17-20 used by the conventional video decoder using the DRAM. Also, the video decoder using the SDRAMS has a memory control section 56 to control the access of the buffers to the bus for the temporary storage of data.
The sequence of memory access required by the macro block units is allocated equally as shown in FIG. 3. However, the bit stream is not compressed by a fixed method, but is compressed by a method designed to suit each macro blocks. As a result, the amount of data required by each block differs. Thus, allocating access to the memory for the different amounts of data in fixed intervals would be inefficient because unnecessary memory access may be given. Moreover, access to a large amount of data at one time would reduce the time required to select the row and column addresses of the SDRAMs which are essential to the SDRAM 57 access.
For a HDTV decoder using frame memories as a external memory, the unit of data to be read out for motion compensation is too small resulting in a random address rather than a continuous address. Generally, access to the data in the SDRAMs 57 is by selecting a row address and shifting the column address as necessary. Unlike the column addresses, the addresses cannot be randomly shifted and must wait to access the data in a different row. Thus, the memories should be allocated in a way which allows access to the data from one row address, if possible.
To allow data access from one row, in case the data is for a HDTV, the data are typically stored in macro block units. However, one row address often is not large enough to store macro blocks located in the same horizontal direction. Consequently, contiguous macro blocks may be stored at a different row, and the memory access efficiency is lowered because of the necessity to select two row addresses in order to read out a data stored in two macro blocks. Furthermore, as illustrated in FIG. 4, contiguous macro blocks MB.sub.n, MB.sub.n+1, MB.sub.m-1 to MB.sub.m+1 may sometimes be stored across three row addresses indicated by the bold line, in which case the data access efficiency is further reduced because the row address must be shifted three times.
To improve data access, a method was suggested by Winzker, Pirsch, and Reimers in "Architecture and Memory Requirements for stand-alone and hierarchical MPEG2 HDTV-Decoders with synchronous DRAMs", IEEE International Symposium on circuits and Systems, Vol. 1, 1995, pp609-612, in which the macro blocks at the boundary area of two rows are repeatedly stored in two rows, as illustrated in FIG. 5. With this method, the macro blocks located at the boundary can be read out from one row, which enhances the memory access efficiency. However, this method is also ineffective when data to access is located across the upper and lower macro blocks because of a need to shift the row addresses, thereby deteriorating the memory access efficiency.